Renesas: reference design supports traffic in 100-Gb class
Renesas Electronics announced a packet header search reference design for 100 Gb communications devices such as routers, switches, and servers. The reference design is comprised of the LLDRAM-III (RMHE41A364AGBG) power-efficient, low-latency memory (LLDRAM), proprietary exact-match search IP, and LLDRAM-III controller IP on an FPGA device, and development support tools. It enables 100 Gb traffic packet header search functionality using 1/15th the number of memory devices than would be required in a configuration employing standard DRAM memory and reduces memory power consumption by 60 percent.
LLDRAM-III is a power-efficient type of low-latency memory from Renesas that supports 400 mega accesses (read or write operations) per second and consumes two watts or less to transfer 57.6 Gb of data. By combining this memory with the newly-developed search algorithm from Renesas, it is possible to process 150 million packet header searches per second, as required for 100 Gb Ethernet, using a single LLDRAM-III device. Performing the same processing with a configuration using a conventional search algorithm and standard DRAM would require around 15 memory devices and consume about five watts of power. The new reference design reduces the number of memory devices to a single LLDRAM-III memory and cuts memory power consumption by 60 percent. This shrinks the memory mounting area by 90 percent and also reduces the number of signal lines between the memory and FPGA by 90 percent, making it possible to configure the system using an FPGA with fewer pins and contributing to reduced overall cost.
The exact-match search IP allows the flexibility of changing the search key length in one-bit units up to a maximum of 143 bits. This makes it possible to accommodate not only conventional MAC address searches but also new communication protocols made possible by advances in network virtualization technology without having to modify the search IP design. Also, the number of search entries can be expanded to two million or even four million by specifying a shorter maximum search key (Note 6) length. This also includes functionality that supports simultaneous output of search results and packet processing rules when the maximum search key length of 143 bits is used, by dividing the search key area and the packet processing rule area appended to the search result.
The development support tools consist of a reference board with proven interoperability between the FPGA and LLDRAM-III, thereby saving time that would otherwise be needed for design and verification, sample design including search IP, a complete verification environment, and a complete evaluation environment. These tools enable users to begin FPGA subsystem design and network equipment design work in parallel, which significantly reduces the development cycle time by around six months (according to calculations by Renesas).
Renesas provides NSEs for the complex communication processing at the 200-Gb class used by external communication interfaces of data centers and backbone communication networks. For communication processing at 100 Gb and below, in applications within data centers having large numbers of ports, Renesas provides a packet header search reference design composed of LLDRAM-III and FPGA. With this new FPGA-based search solution that enables flexible communication and support for rapidly-advancing network technology, Renesas continues its commitment to the communications market with the development of new solutions.