Renesas: reduce development time for search offload engine in 400 Gbps network devices

Renesas Electronics announced the availability of a network search engine (NSE) system-on-chip reference design that eliminates the development time for search offload engine in the communication industry’s fastest-speed class 400-gigabit per second network equipment. Targeting router and switch applications, the reference design comprises a network search engine evaluation board and a Xilinx field-programmable gate array employing a search SoC control IP to simplify the integration of custom functions. Traditional 400 Gbps network processing systems consist of dedicated SoCs such as ASICs or network processors. By using this reference design, system manufacturers can quickly deploy 400 Gbps systems with substantially improved performance for routing and switching applications such as video traffic at endpoints.

The reference design not only provides design data on an evaluation board populated with the R8A20686BG, a Renesas NSE SoC capable of up to two billion packet search operations per second, but also includes the newly developed search SoC control IP and control software that would otherwise require a substantial amount of time to develop.

For system manufacturers, the reference design eliminates the time-consuming process of search offload engine controller development. By integrating Xilinx’s programmable SDNet data plane hardware and NSE controller, this network processing solution is able to accelerate development time in the order of months.

In addition to this 400 Gbps solution, Renesas offers a 200 Gbps design with the same NSE SoC as well as a low-power 100 Gbps solution utilizing LLDRAM-III memory and an FPGA. Renesas’ wide range of search offerings allows system manufacturers to select a solution that best meets their specific requirements and is able to scale with the rapid advancement in network technologies.

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