Cadence: Protium S1 FPGA-based prototyping platform for early software development

Cadence Design Systems announced the new Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity. The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform, thereby delivering 80 percent faster design bring-up on average when compared to typical FPGA prototyping approaches. Utilizing Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier. The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms. Firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control. The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

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