Altreonic: VirtuosoNext Designer implements fine grain space and time partitioning

Altreonic has now ported VirtuosoNext Designer to the Freescale QorIQ T2080/1 processor. The chip has 8 floating point cores implemented as 4 CPUs with a dual register set running at 1.8 GHz. The latest port of VirtuosoNext Designer delivers unprecedented hard real-time capability in the microsecond range in combination with fine grain task level space and time partitioning for embedded safety-critical applications.

In contrast to traditional hypervisor based partitioning schemes, VirtuosoNext protects each application task separately in memory with a real-time response still available in the microseconds range as one expect from using an RTOS.  Moreover, the code size is measured in Kbytes, allowing optimal use of the on-chip caches for best performance.

The small code and low latency are beneficial for all applications. A semaphore loop (using 4 kernel services and 6 context switches) only takes 5.64 microseconds without space partitioning and 6.01 microseconds with space portioning.  This semaphore loop is used as a stress test when measuring the interrupt latency as it continuously invokes the kernel resulting in context switches. The interrupt latency from IRQ to ISR exhibits a histogram with a spread between 286 and 793 nanoseconds without partitioning, which increases to 819 nanoseconds with partitioning enabled. The minimal IRQ to task latency was measured at 2.158 microseconds without partitioning, increasing to 2.262 microseconds (partioning enabled). Under the stress test conditions, the worst case latency remained at 3.848 microseconds.

The fine-grain space partitioning implementation of VirtuosoNext is lightweight both in code size and in runtime impact. The code size of VirtuosoNext without Space Partitioning enabled was measured by building the same application using all available Services (compiled with Os).  The T2080 code size only moderately increases from 1280 bytes to 38504 bytes, which is a moderate increase. Note that the code sizes given include the runtime library of the compiler and the system initialisation.

Besides high performance and productivity, VirtuosoNext Designer is also tailored for safety and security critical applications. As the code is generated as a static image, it eliminates many of the runtime errors that can occur with more traditional dynamic (RT)OS. The packet switching architecture also reduces typical pointer errors and provides extra security. Last but not least, the protected version of VirtuosoNext has built in support for error detection and recovery as well as fine grain space and time partitioning. The latter makes use of the processor’s MMU and allows detecting memory access violations at the Task level. The unique architecture of VirtuosoNext Designer provides the protection of a traditional hypervisor with the real-time responsiveness of an optimised RTOS.

ZES Zimmer on testing advanced power electronics

In this video Bernd Neuner from ZES Zimmer talks to Alix Paultre for Electronic News TV at the 2017 Power Electronics Conference in Nuremberg. The discussion deals with the issues involving test and m...

Weidmüller discusses the need for a better signal and power interface

In this video Rene Arntzen from Weidmüller talks to Alix Paultre of Electronic News TV about the importance of a good signal and power interface for industrial equipment. There is currently no good ...

Mouser talks about the state of engineering development today

In this video Mark Burr-Lonnon and Graham Maggs of Mouser Electronics, a major international electronics distributor, talk to Alix Paultre about the state of engineering development today. With massiv...

Infineon launches a new family of configurable industrial drive boards

In this video Infineon explains their new family of configurable industrial drive boards at SPS-IPC Drives 2017. Intended to enable easy setup and deployment, the XMC-based automation boards can handl...

STMicro explains their STSPIN family of single-chip motor drivers

In this video STMicroelectronics explains their STSPIN single-chip motor drivers at SPS-IPC Drives 2017. The STSPIN family embeds can drive motors efficiently and with high accuracy, with an advanced ...

wholesale jerseys