ANSYS and Synopsys partner to accelerate robust design optimization
ANSYS and Synopsys will enable customers to accelerate the next generation of high-performance computing, mobile and automotive products thanks to a new partnership that will tightly integrate ANSYS’ power integrity and reliability signoff technologies with Synopsys’ physical implementation solution for in-design usage.
Developers of innovative, cost-effective and reliable smart products need to quickly optimize, validate and signoff their designs. While designers have been using ANSYS and Synopsys tools in combination for years, the integrated solution will enable mutual customers to apply power integrity and reliability signoff technologies earlier in the design flow – empowering them to deliver innovative, high-performance and reliable products faster, while reducing power, area and cost.
The integration of ANSYS’ platform for chip power and reliability signoff, ANSYS RedHawk, with Synopsys’ place-and-route solutions, Synopsys IC Compiler II, will provide users earlier signoff accuracy within the Synopsys design environment. This integration will enable rapid design exploration, design weakness detection, optimization and thermal-aware reliability through increased functionality within the place-and-route environment. The in-design power integrity and reliability signoff-driven flow will eliminate late design changes and ensure consistency with final chip-package-system signoff analyses with RedHawk.
Synopsys and ANSYS will also provide a feedback loop between the two-gold standard solutions, Synopsys PrimeTime and ANSYS RedHawk. Voltage-aware timing analysis can be performed rapidly to avoid additional guard-banding and design margining.
