Cadence: Genus synthesis solution improves multi-functional printer SoCs design development

Cadence Design Systems announced that Fuji Xerox used the Cadence Genus Synthesis Solution to improve the development of its multi-functional printer SoCs. The Cadence solution enabled Fuji Xerox to reduce its timing closure schedule more than 50 percent and achieve up to 16 percent area reduction for its sub-blocks, resulting in an eight percent total chip area reduction when compared with its previous solution.

Fuji Xerox employed the Genus Synthesis Solution’s innovative earlyphysical flow, which rapidly models physical effects such as placement androuting from the earliest stages of logic synthesis. This capability helped them minimize gate area of SoC while also meeting performance targets, which led to improved power, performance and area and faster time to market. Additionally, the Cadence solution’s accurate physical effect modeling improved performance correlation to place and route, which allowed Fuji-Xerox design engineers to close the design more easily, reduce the turnaround time (TAT) iterations with their ASIC vendor and shorten the overall development schedule.

The Genus Synthesis Solution is a next-generation RTL synthesis and physical synthesis engine that addresses the productivity challenges faced by SoC designers. It is a part of the Cadence digital design platform that supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

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