Cadence achieves “Fit for Purpose - TCL1” certification in support of ISO 26262 standard

Cadence Design Systems has achieved the industry’s first comprehensive “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification from TÜV SÜD, enabling automotive semiconductor manufacturers, OEMs and component suppliers to meet stringent ISO 26262 automotive safety requirements. To achieve certification, Cadence provided its tool and flow documentation to TÜV SÜD for evaluation, and TÜV SÜD confirmed the Cadence flows are fit for use with ASIL A through ASIL D automotive design projects. The functional safety documentation kits cover analog and mixed-signal, digital front-end and verification, digital implementation and signoff, and PCB flows comprised of nearly 40 tools, offering the broadest EDA-certified tool and flow documentation to support the automotive industry.

Based on the growing importance of EDA solutions for the automotive safety market, both TÜV SÜD and Cadence determined that it was necessary to add a new certification level to further ease the automotive chip designer’s process for achieving ISO 26262 compliance. The Cadence flow-level certification is verifiable via the TÜV SÜD certification database. Under this new certification model, certificates have been issued for each tool flow documentation kit and have a five-year validity. TÜV SÜD plans to review updates to the tool flows and their impact on ISO 26262 compliance at least once a year. 

The tool flow documentation that achieved the TÜV SÜD “Fit for Purpose - TCL1” certification and is included with Cadence Automotive Functional Safety Kits is as follows:

  • PCB design and verification flow: This new certification for PCB design includes everything from design authoring to simulation to physical realization and verification using the Cadence OrCAD, PSpice and Allegro product suites. The high-performance design entry, simulation and layout editing tools included with these suites provide an integrated environment for design engineers to validate the safety specifications against individual circuit specifications for design confidence.
  • Analog/mixed-signal design, implementation and verification flow: This flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Cadence Virtuoso ADE Product Suite and the Spectre Circuit Simulation Platform. The Cadence Virtuoso ADE Verifier provides design engineers with an integrated means to validate the safety specifications against individual circuit specifications for design confidence.
  • Digital implementation and signoff flow: This flow covers RTL-to-GDSII implementation and signoff. The Cadence Virtuoso Liberate Characterization Solution is new to this flow and is incorporated with the 13 other pre-existing tools including the Cadence Innovus Implementation System, Genus Synthesis Solution, Modus Test Solution, Tempus Timing Signoff Solution, Quantus QRC Extraction Solution and Voltus IC Power Integrity Solution for the implementation and signoff of automotive designs.

The digital front-end design and verification flow’s documentation kit has been evaluated and confirmed to be compliant with ISO 26262, and is expected to achieve certification during Q4 2017. The flow documentation kit covers specification to RTL design to verification. The front-end digital tools include the Cadence Genus Synthesis Solution and Conformal Equivalence Checker. Functional and safety verification capabilities are provided by the Cadence Verification Suite, which includes the Cadence JasperGold Formal Verification Platform, Xcelium Parallel Logic Simulator (to be added to the flow documentation in Q4 2017), Palladium Z1 Enterprise Emulation Platform, Protium FPGA-Based Prototyping Platform, vManager Metric-Driven Signoff Platform and the Indago Debug Platform (to be added to the flow documentation in Q4 2017). 

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