Cadence: Xcelium logic simulation technology for Arm-based servers

Cadence Design Systems and Arm announced early access to the Cadence Xcelium Parallel Logic Simulation on Arm-based servers, providing a first-of-its-kind low-power, high-performance simulation solution for the electronics industry.

Prior to manufacturing, verifying that SoC designs function correctly is a massive task accounting for over 70 percent of the EDA compute workload, and is a key driver for growth and transformation of the datacenter. The Xcelium simulation runs natively on Arm-based servers delivering significant power and capacity benefits, executing both high-throughput and long-latency workloads to reduce overall SoC verification time and costs.

The Xcelium simulator, part of the Cadence Verification Suite, improves runtime through optimized single-core simulation and innovative multi-core simulation. It provides up to 2X speedup for single-core, and 3X to 10X speedup for multi-core simulation tasks compared to previous simulators, reducing long-latency SoC tests and shortening overall time to market. Running the Xcelium simulator on Arm-based servers allows systems and semiconductor companies to best utilize the available cores within those servers to achieve the fast verification that advanced-node designs require. Additionally, the simulator provides automatic partitioning of design and verification testbench codes for fast execution on multi-core servers.

Arm-based servers deliver the high-core density needed to enable accelerated simulation, allowing designers to complete their verification faster. When running single-core workloads, Arm-based servers are able to execute more Xcelium jobs within the same datacenter footprint. When running long-latency workloads, they are able to provide more cores for the parallel simulation. Together, the Xcelium simulator running on Arm-based servers maintain the throughput required to develop leading-edge SoCs and also reduce the total cost of ownership for the datacenter.

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