Cadence announces PCI Express 5.0 Verification IP with TripleCheck technology

Cadence Design Systems announced the availability of the industry’s first Verification IP (VIP) in support of the new PCI Express5.0 architecture. The Cadence VIP incorporates TripleCheck technology, which lets designers quickly and thoroughly complete functional verification of server and storage system-on-chip designs based on the PCIe 5.0 specification, providing designers with added confidence that designs can function as originally intended.

The differentiated, proven Cadence VIP has supported all recent PCIe standards and has been further optimized for the new 5.0 specification. Adopters of the PCIe 5.0 specification have access to the Cadence TripleCheck technology, which provides a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with thousands of ready-to-run tests to ensure compliance with the specification. This enables designers to save time and deliver higher quality end-products. Additionally, designers have access to the Indago Protocol Debug App, which provides protocol-specific interactions between the design, the VIP and the testbench to find the root cause of any design bugs.

The Cadence VIP with TripleCheck technology is part of the Cadence Verification Suite and is optimized for Xcelium Parallel Logic Simulation, along with supported third-party simulators. The PCIe 5.0 VIP supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

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